The present disclosure relates to integrated circuit design and more particularly to wiring layout in order to maximize device performance and reliability.
Electronic devices, particularly integrated circuits, comprise a large number of components fabricated by layering several different materials onto a silicon wafer. In order for the components to function as an electronic device, they are selectively, electrically connected to one another. Metal lines are utilized to electrically connect components. The metal lines provide electrical connection within a layer, while vias connect different metallization and via layers. It is important that a good connection between the via and metal line exists in order to ensure that the proper amount of current is carried with minimal resistance between the connected components.
Unfortunately, a mechanism that causes reliability problems seen in integrated circuits results from time-dependent gate dielectric breakdown (or time dependent dielectric breakdown—TDDB). Time dependent dielectric breakdown is a failure mechanism that occurs when the dielectric breaks down as a result of long-time application of relatively low electric field (as opposed to immediate breakdown, which is caused by strong electric field). The breakdown is caused by formation of a conducting path through the dielectric to an interconnect on a different voltage net due to electron tunneling current. This typically occurs when interconnects are operated close to or beyond their specified operating voltages.
In addition, the maximum voltage (Vmax) of the technology defines the space between features on the chip, such as between a contact via and a polysilicon line layer (CA/PC), between metallization lines (M1/M1), etc., due to TDDB. This limits how conductive the contact via, the metallization line, etc. can be. Accordingly, the Vmax limits how high in performance the chip can reach.